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acpm-7355 umts dual-band 4x5mm power ampli?er module (band2/band5) data sheet description the acpm-7355 is a dual-band pam (power ampli?er module) designed for umts band2 and band5. the acpm- 7355 meets stringent umts linearity requirements. the 4mmx5mm form factor 14-pin surface mount package is self contained, incorporating 50ohm input and output matching networks the acpm-7355 features 5 th generation of coolpam circuit technology which supports 3 modes C bypass, mid and high power modes. the coolpam is stage bypass technology which enables power ampli?er to lower power consumption. active bypass feature is added to 5 th generation to enhance power added e?ciency at low output range and this technology extends talk time of mobiles more by further saving power ampli?ers current consumption. the power ampli?er is manufactured on an advanced ingap hbt (hetero-junction bipolar transistor) mmic (microwave monolithic integrated circuit) technology o?ering state-of-the-art reliability, temperature stability and ruggedness. the module is housed in a cost e?ective, small and thin 4x5mm package. features dual-band pa (band2 and band5) small size (4x5mm) thin package (1.0mm typ) excellent linearity 3-mode power control bypass / mid power mode / high power mode high e?ciency at max output power 14-pin surface mounting package internal 50ohm matching networks for both rf input and output lead-free, rohs compliant, green applications umts band2 and band5 ordering information part number number of devices container ACPM-7355-TR1 1000 178mm (7) tape/reel acpm-7355-blk 100 bulk block diagram rfin_lb rfin_hb rfout_lb rfout_hb bias circuit & control logic bypass circuit impedance transformer bypass circuit impedance transformer output match vcc1 vcc2 vmode vbp ven_lb ven_hb input match & power divider output match input match & power divider
2 recommended operating condition description min typ max unit dc supply voltage 3.2 3.4 4.2 v enable voltage (ven_low, ven_hi) low high 0 1.35 0 2.6 0.5 3.1 v v mode control voltage (vmode) low high 0 1.35 0 2.6 0.5 3.1 v v bypass control voltage (vbp) low high 0 1.35 0 2.6 0.5 3.1 v v operating frequency band5 band2 824 1850 849 1910 mhz mhz ambient temperature -30 25 85 c operating logic table power mode ven_low, ven_hi vbp vmode pout (rel99) pout (hsdpa, hsupa mpr=0db) high power mode high low low ~27.0dbm (band5) ~27.5dbm(band2) ~26.0dbm (band5) ~ 26.5dbm (band2) mid power mode high low high ~17dbm ~16dbm bypass mode high high high ~8dbm ~7dbm shut down mode low low low C C absolute maximum ratings no damage assuming only one parameter is set at limit at a time with all other parameters set at or below typical value. operation of any single parameter outside these conditions with the remaining parameters set at or below typical values may result in permanent damage. description min typ max unit associated pins rf input power (high power mode) output power (bypass mode) output power (mid power mode) 010 10 18 dbm rfin_hi, rfin_low rfout_hi, rfout_low rfout_hi, rfout_low dc supply voltage 0 3.4 5.0 v vcc1, vcc2 enable voltage 0 2.6 3.3 v ven_low, ven_hi mode control voltage 0 2.6 3.3 v vmode bypass control 0 2.6 3.3 v vbp storage temperature -55 25 +125 c
3 electrical characteristics in band5 C conditions: vcc = 3.4v, ven_low = 2.6v, t = 25c, zin/zout = 50ohm C signal con?guration: 3gpp (dpcch+1dpdch) up-link unless speci?ed otherwise characteristics condition min typ max unit operating frequency range 824 C 849 mhz gain high power mode, pout=27dbm 24 28.5 db mid power mode, pout=17dbm 15 19.5 db bypass power mode, pout=8dbm 10 15 db total supply current high power mode, pout=27dbm 380 440 ma mid power mode, pout=17dbm 70 100 ma bypass power mode, pout=8dbm 13.5 20 ma quiescent current high power mode 70 95 120 ma mid power mode 10 20 30 ma bypass mode 2 3.4 5 ma enable current high power mode 10 a mid power mode 10 a bypass mode 10 a mode control current mid power mode 5 a bypass mode 5 a bypass control current 100 a total current in power-down mode ven_low=0v, vmode=0v, vbp=0v 0.2 5 a adjacent channel leakage ratio 5 mhz o?set 10 mhz o?set high power mode, pout=27dbm -42 -55 -36 -46 dbc dbc 5 mhz o?set 10 mhz o?set high power mode, pout=26dbm (hsdpa, hsupa mpr=0db) -40 -51 -35 -46 dbc dbc 5 mhz o?set 10 mhz o?set mid power mode, pout=17dbm -49 -61 -36 -46 dbc dbc 5 mhz o?set 10 mhz o?set mid power mode, pout=16dbm (hsdpa, hsupa mpr=0db) -47 -59 -36 -46 dbc dbc 5 mhz o?set 10 mhz o?set bypass mode, pout=8dbm -41 -58 -36 -46 dbc dbc 5 mhz o?set 10 mhz o?set bypass mode, pout=7dbm (hsdpa, hsupa mpr=0db) -40 -58 -36 -46 dbc dbc harmonic suppression second third high power mode, pout=27dbm -37 -72 -30 -40 dbc dbc input vswr 2:1 2.5:1 stability (spurious output) in-band load vswr <= 5:1, all phase out of band load vswr <= 10:1, all phase forwarded power ?xed -60 dbc rx band noise power -135.5 -133 dbm/hz gps band noise -156 -140 dbm/hz phase discontinuity mid power mode high power mode, at pout=17dbm low power mode mid power mode, at pout=8dbm 36 deg deg ruggedness no damage pout<27dbm, pin<10dbm, all phase high power mode 10:1 vswr
4 electrical characteristics in band2 C conditions: vcc = 3.4v, ven_hi = 2.6v, t = 25c, zin/zout = 50ohm C signal con?guration: 3gpp (dpcch+1dpdch) up-link unless speci?ed otherwise characteristics condition min. typ. max. unit operating frequency range 1850 C 1910 mhz gain high power mode, pout=27.5dbm 24 28 db mid power mode, pout=17dbm 15 21.5 db bypass power mode, pout=8dbm 9 13.5 db total supply current high power mode, pout=27.5dbm 440 500 ma mid power mode, pout=17dbm 75 105 ma bypass power mode, pout=8dbm 12.5 20 ma quiescent current high power mode 75 100 125 ma mid power mode 15 25 35 ma bypass mode 1.5 3 4.5 ma enable current high power mode 10 a mid power mode 10 a bypass mode 10 a mode control current mid power mode 5 a bypass mode 5 a bypass control current 100 a total current in power-down mode ven_hi=0v, vmode=0v, vbp=0v 0.2 5 a adjacent channel leakage ratio 5 mhz o?set 10 mhz o?set high power mode, pout=27.5dbm -41 -51 -36 -46 dbc dbc 5 mhz o?set 10 mhz o?set high power mode, pout=26.5dbm (hsdpa, hsupa mpr=0db) -39 -52 -35 -46 dbc dbc 5 mhz o?set 10 mhz o?set mid power mode, pout=17dbm -50 -64 -36 -46 dbc dbc 5 mhz o?set 10 mhz o?set mid power mode, pout=16dbm (hsdpa, hsupa mpr=0db) -49 -62 -36 -46 dbc dbc 5 mhz o?set 10 mhz o?set bypass mode, pout=8dbm -43 -54 -36 -46 dbc dbc 5 mhz o?set 10 mhz o?set bypass mode, pout=7dbm (hsdpa, hsupa mpr=0db) -41 -55 -36 -46 dbc dbc harmonic suppression second third high power mode, pout=27.5 dbm -52 -74 -30 -40 dbc dbc input vswr 2:1 2.5:1 stability (spurious output) in-band load vswr <= 5:1, all phase out of band load vswr <= 10:1, all phase forwarded power ?xed -60 dbc rx band noise power -138 -133 dbm/hz gps band noise -140 -136 dbm/hz phase discontinuity mid power mode high power mode, at pout=17dbm low power mode mid power mode, at pout=8dbm 16 21 deg deg ruggedness no damage pout<27.5dbm, pin<10dbm, all phase high power mode 10:1 vswr
5 hsdpa signal con?guration used: 3gpp ts 34.121-1 annex c (normative e): measurement channels c.10.1 ul reference measurement channel for hsdpa tests table c.10.1.4: values for transmitter characteristics tests with hs-dpcch sub-test 2 (cm=1.0, mpr=0.0) hsupa signal con?guration used: 3gpp ts 34.121-1 annex c (normative): measurement channels c.11.1 ul reference measurement channel for e-dch tests table c.11.1.3: values for transmitter characteristics tests with hs-dpcch and e-dch sub-test 1 (cm=1.0, mpr=0.0)
6 characteristics data of band5 (vcc = 3.4v, ven_low = 2.6, vbp, vmode = 0v or 2.6v, t = 25c, zin/zout = 50ohm, rel99) total current vs. output power gain vs. output power adjacent channel power ratio 1 vs. output power adjacent channel power ratio 2 vs. output power power added e?ciency vs. output power 0 50 100 150 200 250 300 350 400 450 500 -5 0 5 10 15 20 25 30 pout (dbm) current (ma) 824mhz, 3.4v 837mhz, 3.4v 847mhz, 3.4v -60 -55 -50 -45 -40 -35 -30 -5 0 5 10 15 20 25 30 pout (dbm) aclr1 (dbc) 0 5 10 15 20 25 30 35 40 45 50 -5 0 5 10 15 20 25 30 pout (dbm) pae(%) 0 5 10 15 20 25 30 35 -5 0 5 10 15 20 25 30 pout (dbm) gain (db) -70 -65 -60 -55 -50 -45 -40 -5 0 5 10 15 20 25 30 pout (dbm) aclr2 (dbc) 824mhz, 3.4v 837mhz, 3.4v 847mhz, 3.4v 824mhz, 3.4v 837mhz, 3.4v 847mhz, 3.4v 824mhz, 3.4v 837mhz, 3.4v 847mhz, 3.4v 824mhz, 3.4v 837mhz, 3.4v 847mhz, 3.4v
7 characteristics data of band2 (vcc = 3.4v, ven_hi = 2.6, vbp and vmode = 0v or 2.6v, t = 25c, zin/zout = 50ohm, rel99) total current vs. output power gain vs. output power adjacent channel power ratio 1 vs. output power adjacent channel power ratio 2 vs. output power power added e?ciency vs. output power 0 50 100 150 200 250 300 350 400 450 500 -5 0 5 10 15 20 25 30 pout (dbm) current (ma) 1850m hz, 3.4v 1880m hz, 3.4v 1910m hz, 3.4v -60 -55 -50 -45 -40 -35 -30 -5 0 5 10 15 20 25 30 pout (dbm) aclr1 (dbc) 0 5 10 15 20 25 30 35 40 45 50 -5 0 5 10 15 20 25 30 pout (dbm) pae(%) 0 5 10 15 20 25 30 35 -5 0 5 10 15 20 25 30 pout (dbm) gain (db) -70 -65 -60 -55 -50 -45 -40 -5 0 5 10 15 20 25 30 pout (dbm) aclr2 (dbc) 1850m hz, 3.4v 1880m hz, 3.4v 1910m hz, 3.4v 1850m hz, 3.4v 1880m hz, 3.4v 1910m hz, 3.4v 1850m hz, 3.4v 1880m hz, 3.4v 1910m hz, 3.4v 1850m hz, 3.4v 1880m hz, 3.4v 1910m hz, 3.4v
8 footprint all dimensions are in millimeters package dimensions all dimensions are in millimeters x-ray top view pin descriptions pin # name description 1 rfin_low band5 rf input 2 vmode mode control 3 vbp bypass control 4 vcc1 supply voltage 5 ven_low band5 pa enable 6 ven_hi band2 pa enable 7 rfin_hi band2 rf input 8 rfout_hi band2 rf output 9 gnd ground 10 gnd ground 11 vcc2 supply voltage 12 gnd ground 13 gnd ground 14 rfout_low band5 rf output 5 0.1 2 3 4 4 0.1 pin 1 mark 1 0.6 1.0 0.05 5 6 7 13 12 11 14 10 9 8
9 marking speci?cation pin 1 mark avago acpm-7355 pyyww aaaaa manufacturing part number lot number p manufacturing info yy manufacturing year ww work week aaaaa assembly lot number coolpam avago technologies coolpam is stage-bypass pa tech- nology which saves more power compared with conven- tional pa. with this technology, the acpm-7355 has very low quiescent current, and e?ciencies at low and medium output power ranges are high. incorporation of bias circuit the acpm-7355 has internal bias circuit, which removes the need for external constant voltage source (ldo). pa on/o? is controlled by ven. this is digitally control pin. 3-mode power control with two mode control pins the acpm-7355 supports three power modes ( bypass power mode/mid power mode/high power mode) with two mode control pins (vmode and vbp). this control scheme enables the acpm-7355 to save power consump- tion more, which accordingly gives extended talk time. pdf (probability density function) in the ?gure 1 showing distribution of output power of mobile in real ?eld gives motivation for stage-bypass pa. output power is less than 16dbm for most of operating time (during talking), so it is important to save power consumption at low and medium output power ranges. figure 1 . pdf and current average current & talk time average current consumed by pa can be calculated by summing up current at each output power weighted with probability. so it is expressed with integration of multipli- cation of current and probability at each output power. average current = (pdf x current)dp talk time is extended more as average current consump- tion is lowered.
10 mode control pins vmode and vbp are digitally controlled by baseband and they control the operating mode of the pa. the logic table is summarized in the below table. these pins do not require constant voltage for interface. power mode ven_low, ven_hi vbp vmode pout (rel99) pout (hsdpa, hsupa mpr=0db) high power mode high low low ~27.0dbm (band5) ~27.5dbm(band2) ~26.0dbm (band5) ~ 26.5dbm (band2) mid power mode high low high ~17dbm ~16dbm bypass mode high high high ~8dbm ~7dbm shut down mode low low low C C operating logic table. figure 2. icc comparison of cp5 to cp4 (avago coolpam) umts pa performance comparison C coolpam 4 and coolpam 5 the 5 th generation of coolpam technology, acpm-7355 can dramatically reduce icc down to 3ma at bypass mode, which improves overall talk time and battery usage time of handset more compared with the cp4. 0 50 100 150 200 250 300 350 400 450 current (ma) cp5 cp4 pout(dbm) -10 0 10 20 30 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 pout(dbm) current (ma) cp5 cp4
11 application on mobile phone board the ?gure 3 shows an application example in mobile. c5 and c6 should be placed close to pin4 and pin11. bypass cap c1, c2, c3 and c4 should be also placed nearby from pin2, pin3, pin5 and pin6, respectively. the length of post-pa trans- mission line should be minimized to reduce line loss. figure 3. peripheral circuits pcb layout and part placement on phone board figure 4. pcb guideline on phone board c4 acpm-7355 low in vmode vbp vcc1 ven_l ven_h high in c2 rf in high c1 tx ?lter c9 c7 v batt c5 c6 output matching circuit c13 c12 l2 coupler rf out high low out gnd gnd vcc2 gnd gnd high out tx ?lter c8 rf in low c3 c11 c10 l1 coupler rf out low pa_on_low band pa_r1 pa_r0 pa_on _high band 1 4 via hole 3 2 notes: 1. to prevent voltage drop, make the bias lines as wide as possible (pink line). 2. use many via holes to fence o? pa rf input and output traces for better isolation. output signal of the pa should be isolated from input signal and the receive signal. output signal should not be fed into pa input. (green line) 3. use via holes to connect outer ground plates to internal ground planes. they help heat spread out more easily and accordingly the board temperature can be lowered. they also help to improve rf stability (yellow square). 4. pa which has a ground slug requires many via holes which go through all the layers (red square).
12 metallization solder mask opening solder paste stencil aperture pcb design guidelines the recommended pcb land pattern is shown in ?gures on the left side. the substrate is coated with solder mask between the i/o and conductive paddle to protect the gold pads from short circuit that is caused by solder bleeding/bridging. stencil design guidelines a properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the pcb pads. the recommended stencil layout is shown here. reducing the stencil opening can potentially generate more voids. on the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the i/o pads or conductive paddle to adjacent i/o pads. considering the fact that solder paste thickness will directly a?ect the quality of the solder joint, a good choice is to use laser cut stencil composed of 0.100mm(4mils) or 0.127mm(5mils) thick stainless steel which is capable of producing the required ?ne stencil outline. ? 0.3 via on 0.6 pitch 0.60 0.40 0.73 0.25 0.33 0.50 0.70 0.55 0.50 0.73 2.40 2.30 0.60 0.40 0.73 0.50 2.00 2.10
13 evaluation board schematic evaluation board description 1 rfin_low 2 vmode 3 vbp 4 vcc1 rfout_low 14 gnd 12 vcc2 11 band5 rf in vmode vcc2 band2 rf out c6 100pf gnd 13 5 ven_low 6 ven_hi 7 rfin_hi gnd 10 rfout_hi 8 gnd 9 vbp c5 100pf vcc1 c3 1000pf c4 2.2uf ven_band5 c2 100pf ven_band2 c1 100pf band2 rf in c8 2.2uf c7 1000pf band5 rf out avago acpm-7355 pyyww aaaaa c4 c7 c8
14 tape and reel information dimension list dimension millimeter a0 4.400.10 b0 4.400.10 k0 1.700.10 d0 1.550.05 d1 1.600.10 p0 4.000.10 p1 8.000.10 dimension millimeter p2 2.000.05 p10 40.000.20 e 1.750.10 f 5.500.05 w 12.000.30 t 0.300.05 avago acpm-735 pyyww aaaaa tape and reel format C 4 mm x 5 mm
15 plastic reel format (all dimensions are in millimeters) reel drawing notes: 1. reel shall be labeled with the following information (as a minimum). a. manufacturers name or symbol b. avago technologies part number c. purchase order number d. date code e. quantity of units 2. a certi?cate of compliance (c of c) shall be issued and accompany each shipment of product. 3. reel must not be made with or contain ozone depleting materials. 4. all dimensions in millimeters (mm) 50 min. 12.4 +2.0 -0.0 18.4 max. 25 min wide (ref) slot for carrier tape insertion for attachment to reel hub (2 places 180 apart) back view front view 178 shading indicates thru slots +0.4 -0.2 21.0 0.8 13.0 0.2 1.5 min.
16 handling and storage esd (electrostatic discharge) electrostatic discharge occurs naturally in the environ- naturally in the environ- naturally in the environ- ment. with the increase in voltage potential, the outlet of neutralization or discharge will be sought. if the acquired discharge route is through a semiconductor device, de- through a semiconductor device, de- through a semiconductor device, de- de- de- structive damage will result. esd countermeasure methods should be developed and used to control potential esd damage during handling in a factory environment at each manufacturing site. msl (moisture sensitivity level) plastic encapsulated surface mount package is sensitive to damage induced by absorbed moisture and temperature. avago technologies follows jedec standard j-std 020b. each component and package type is classi?ed for moisture sensitivity by soaking a known dry package at moisture classi?cation level and floor life msl level floor life (out of bag) at factory ambient =< 30c/60% rh or as stated 1 unlimited at =< 30c/85% rh 2 1 year 2a 4 weeks 3 168 hours 4 72 hours 5 48 hours 5a 24 hours 6 mandatory bake before use. after bake, must be re?owed within the time limit speci?ed on the label note : 1. the msl level is marked on the msl label on each shipping bag. various temperatures and relative humidity, and times. after soak, the components are subjected to three con- subjected to three con- subjected to three con- secutive simulated re?ows. the out of bag exposure time maximum limits are deter- mined by the classi?cation test describe below which cor- responds to a msl classi?cation level 6 to 1 according to the jedec standard ipc/jedec j-std-020b and j-std-033. acpm-7355 is msl3. thus, according to the j-std-033 p.10, the maximum manufacturers exposure time (met) for this part is 168 hours. after this time period, the part would need to be removed from the reel, de-taped and then re-baked. msl classi?cation re?ow temperature for the acpm-7355 is targeted at 260c +0/-5c. figure and table on next page show typical smt pro?le for maximum temperature of 260 +0/-5c.
17 re?ow pro?le recommendations typical smt re?ow pro?le for maximum temperature = 260 +0/-5c 25 time temperature tp t l tp t l t 25c to peak ramp-up ts ts min ramp-down preheat critical zone t l to tp ts max typical smt re?ow pro?le for maximum temperature = 260 +0/ -5c pro?le feature sn-pb solder pb-free solder average ramp-up rate (tl to tp) 3c/sec max 3c/sec max preheat C temperature min (tsmin) C temperature max (tsmax) C time (min to max) (ts) 100c 150c 60-120 sec 150c 200c 60-120 sec tsmax to tl C ramp-up rate 3c/sec max time maintained above: C temperature (tl) C time (tl) 183c 60-150 sec 217c 60-150 sec peak temperature (tp) 240 +0/-5c 260 +0/-5c time within 5c of actual peak temperature (tp) 10-30 sec 20-40 sec ramp-down rate 6c/sec max 6c/sec max time 25c to peak temperature 6 min max. 8 min max.
18 storage condition packages described in this document must be stored in sealed moisture barrier, antistatic bags. shelf life in a sealed moisture barrier bag is 12 months at <40c and 90% relative humidity (rh) j-std-033 p.6. out-of-bag time duration after unpacking the device must be soldered to the pcb within 168 hours with factory conditions <30c and 60% rh as listed in the table 5-1 on the j-std-020d p.6. baking it is not necessary to re-bake the part if both conditions (storage conditions and out-of bag conditions) have been satis?ed. baking must be done if at least one of the condi- tions above has not been satis?ed. the baking conditions are listed in the table 4-1 on the j-std-033 p.8. caution tape and reel materials typically cannot be baked at the temperature described above. if out-of-bag exposure time is exceeded, parts must be baked for a longer time at low temperatures, or the parts must be de-reeled, de- taped, re-baked and then put back on tape and reel. (see moisture sensitive warning label on each shipping bag for information of baking). board rework component removal, rework and remount if a component is to be removed from the board, it is recommended that localized heating be used and the maximum body temperatures of any surface mount component on the board not exceed 200c. this method will minimize moisture related component damage. if any component temperature exceeds 200c, the board must be baked dry per 4-2 prior to rework and/or component removal. component temperatures shall be measured at the top center of the package body. any smd packages that have not exceeded their ?oor life can be exposed to a maximum body temperature as high as their speci?ed maximum re?ow temperature. removal for failure analysis not following the above requirements may cause moisture/ re?ow damage that could hinder or completely prevent the determination of the original failure mechanism. baking of populated boards some smd packages and board materials are not able to withstand long duration bakes at 125c. examples of this are some fr-4 materials, which cannot withstand a 24 hr bake at 125c. batteries and electrolytic capacitors are also temperature sensitive. with component and board temperature restrictions in mind, choose a bake tem- perature from table 4-1 in j-std 033; then determine the appropriate bake duration based on the component to be removed. for additional considerations see ipc-7711 andipc-7721. derating due to factory environmental conditions factory ?oor life exposures for smd packages removed from the dry bags will be a function of the ambient envi- ronmental conditions. a safe, yet conservative, handling approach is to expose the smd packages only up to the maximum time limits for each moisture sensitivity level as shown in table of moisture classi?cation level and floor life. this approach, however, does not work if the factory humidity or temperature is greater than the testing conditions of 30c/60% rh. a solution for address- ing this problem is to derate the exposure times based on the knowledge of moisture di?usion in the component package materials ref. jesd22-a120). recommended equivalent total ?oor life exposures can be estimated for a range of humidities and temperatures based on the nominal plastic thickness for each device. table on follwoing page lists equivalent derated ?oor lives for humidities ranging from 20-90% rh for three tempera- ture, 20c, 25c, and 30c. this table is applicable to smds molded with novolac, biphenyl or multifunctional epoxy mold compounds. the following assumptions were used in calculating this table: 1. activation energy for di?usion = 0.35ev (smallest known value). 2. for 60% rh, use di?usivity = 0.121exp (-0.35ev/kt) mm2/s (this used smallest known di?usivity @ 30c). 3. for >60% rh, use di?usivity = 1.320exp ( -0.35ev/kt) mm2/s (this used largest known di?usivity @ 30c).
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2009 avago technologies. all rights reserved. av02-2016en - october 23, 2009 recommended equivalent total floor life (days) @ 20c, 25c & 30c, 35c for ics with novolac, biphenyl and multifunctional epoxies (re?ow at same temperature at which the component was classi?ed) maximum percent relative humidity maximum percent relative humidity package type and body thickness moisture sensitivity level 5% 10% 20% 30% 40% 50% 60% 70% 80% 90% body thickness 3.1 mm including pqfps >84 pin, plccs (square) all mqfps or all bgas 1 mm level 2a 94 124 167 231 44 60 78 103 32 41 53 69 26 33 42 57 16 28 36 47 7 10 14 19 5 7 10 13 4 6 8 10 35c 30c 25c 20c level 3 8 10 13 17 7 9 11 14 6 8 10 13 6 7 9 12 6 7 9 12 4 5 7 10 3 4 6 8 3 4 5 7 35c 30c 25c 20c level 4 3 5 6 8 3 4 5 7 3 4 5 7 2 4 5 7 2 3 5 7 2 3 4 6 2 3 3 5 1 2 3 4 1 2 3 4 35c 30c 25c 20c level 5 2 4 5 7 2 3 5 7 2 3 4 6 2 2 4 5 1 2 3 5 1 2 3 4 1 2 2 3 1 1 2 3 1 1 2 3 35c 30c 25c 20c level 5a 1 2 3 5 1 1 2 4 1 1 2 3 1 1 2 3 1 1 2 3 1 1 2 2 1 1 1 2 1 1 1 2 1 1 1 2 35c 30c 25c 20c body 2.1 mm thickness <3.1 mm including plccs (rectangular) 18-32 pin soics (wide body) soics 20 pins, pqfps 80 pins level 2a 58 86 148 30 39 51 69 22 28 37 49 3 4 6 8 2 3 4 5 1 2 3 4 35c 30c 25c 20c level 3 12 19 25 32 9 12 15 19 7 9 12 15 6 8 10 13 5 7 9 12 2 3 5 7 2 2 3 5 1 2 3 4 35c 30c 25c 20c level 4 5 7 9 11 4 5 7 9 3 4 5 7 3 4 5 6 2 3 4 6 2 3 4 5 1 2 3 4 1 2 2 3 1 1 2 3 35c 30c 25c 20c level 5 3 4 5 6 2 3 4 5 2 3 3 5 2 2 3 4 2 2 3 4 1 2 3 4 1 1 2 3 1 1 1 3 1 1 1 2 35c 30c 25c 20c level 5a 1 2 2 3 1 1 2 2 1 1 2 2 1 1 2 2 1 1 2 2 1 1 2 2 1 1 1 2 0.5 0.5 1 2 0.5 0.5 1 1 35c 30c 25c 20c body thickness <2.1 mm including soics <18 pin all tqfps, tsops or all bgas <1 mm body thickness level 2a 17 28 1 1 2 2 0.5 1 1 2 0.5 1 1 1 35c 30c 25c 20c level 3 8 11 14 20 5 7 10 13 1 1 2 2 0.5 1 1 2 0.5 1 1 1 35c 30c 25c 20c level 4 7 9 12 17 4 5 7 9 3 4 5 7 2 3 4 6 1 1 2 2 0.5 1 1 2 0.5 1 1 1 35c 30c 25c 20c level 5 7 13 18 26 3 5 6 8 2 3 4 6 2 2 3 5 1 2 3 4 1 1 2 2 0.5 1 1 2 0.5 1 1 1 35c 30c 25c 20c level 5a 7 10 13 18 2 3 5 6 1 2 3 4 1 1 2 3 1 1 2 2 1 1 2 2 1 1 1 2 0.5 1 1 2 0.5 0.5 1 1 35c 30c 25c 20c

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